Many computing systems include multiple processors and input/output (I/O) agents that interface with I/O and storage devices, and also include coherent memories, which can be a coherent cache for multiple processors. Since one or more caches are often included in these multiple processors, a coherent cache means that the processor shares its cache with other agents that may request access to the cache (e.g., other processors or I/O agents).
When a computing system includes multiple coherent cache memories and multiple requesting agents like the multiple processors and I/O agents, a conflict may occur when two agents request access to a cache line at the same time. To alleviate this problem, a system of arbitrating for access to a specific cache line between multiple request agents is typically accomplished using a cache coherency protocol. Oftentimes, a central entity such as a directory is used to maintain cache coherency by storing entries indicating location and state of various cache lines present in one or more of the cache memories. Cache coherency algorithms define the behavior of reads and writes to the same memory location. The coherence of caches is obtained if the following conditions are met: (1) a read made by a processor P to a location X that follows a write by the same processor P to X, with no writes of X by another processor occurring between the write and the read instructions made by P, must always return the value written by P; (2) a read made by a processor P1 to location X that follows a write by another processor P2 to X must return the written value made by P2 if no other writes to X made by any processor occur between the two accesses; and (3) a read made by a processor P1 to location X that follows a write by another processor P2 to X must return the written value made by P2 if no other writes to X made by any processor occur between the two accesses
However, as the number of caches and/or requesting agents increases in a computing system, the complexity of maintaining cache coherency, and the number of messages required between these agents also increases as the cache coherency protocol must be adapted to the newly scaled computing system. Still further, to maintain coherency, an increased number of messages must be sent, which increases traffic on the interconnect, reducing bandwidth for other communications, and further leading to latencies in replying to requests for data.